1. Field of the Invention
The present invention relates to a biasing circuit, and more particularly to a biasing circuit with a compensation circuit for stabilizing the output thereof.
2. Description of Related Art
Phase Lock Loop (PLL) has been widely used in the design of integrated circuits, especially in frequency combination, clock feedback and data feedback. The key element in the PLL is Voltage Control Oscillator (VCO) and the VCO directly affects the performance of the PLL.
FIG. 5 is a circuit block diagram showing a prior art VCO. Referring to FIG. 5, the VCO 500 comprises a replica biasing circuit 502, a voltage/current converter 504, a ring oscillator 508, a differential circuit 510 and a reference voltage generating circuit 532.
FIG. 6 is a schematic drawing showing a prior art VCO. The biasing circuit 502 comprises a comparison circuit 516 and a delay circuit 514. The delay circuit 514 comprises a variable current source 522, a first transistor M51, a first resistor circuit 524, a second transistor M52 and a second resistor circuit 526. The variable current source 522 receives the input current and an operational voltage, and outputs a variable current from a current output terminal of the variable current source 522. The first transistor M51 comprises a drain terminal, a source terminal and a gate terminal, wherein the source terminal is coupled to the current output terminal of the variable current source 522, the gate terminal is grounded and the drain terminal is coupled to the first resistor circuit 524. The first resistor circuit 524 comprises a first terminal, a second terminal and a third terminal, wherein the second terminal is grounded and the third terminal is coupled to the output terminal of the comparison circuit 516. The resistance of the first resistor circuit 524 varies with the comparison signal.
The second transistor M52 comprises a source terminal, a drain terminal and a gate terminal, wherein the source terminal is coupled to the current output terminal of the variable current source 522 and the gate terminal is coupled to the third input terminal of the delay circuit 544, i.e. the reference voltage. The second resistor circuit 526 comprises a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the drain terminal of the second transistor M52, the second terminal is grounded and the third terminal is coupled to the output terminal of the comparison circuit 516. The resistance of the first resistor circuit 126 varies with the comparison signal.
The first output terminal of the delay circuit 514 is disposed between the first transistor M51 and the first resistor circuit 524, and the second output terminal of the delay circuit 514 is disposed between the second transistor M52 and the second resistor circuit 526.
In the prior art technology, the voltage/current converter 504 receives and converts the input voltage into an input current. The voltage/current converter 504 outputs the input current to the replica biasing circuit 502 and the ring oscillator 508. The delay circuit 514 generates the first differential voltage according to the reference voltage output from the reference voltage generating circuit 532 and the current provided by the variable current source 522. The comparison circuit 516 outputs the comparison signal to the first resistor circuit 524 and the second resistor circuit 526 according to the reference voltage and the first differential voltage. The comparison signal from the comparison circuit 516 is also fed to the ring oscillator 508. The ring oscillator 508 and the differential circuit 510 output the clock signal according to the input current and the comparison signal from the comparison circuit 516.
FIGS. 7A and 7B are small-signal analysis curves of the prior art replica biasing circuit. The DC gain is equal to 71.36 dB. The whole frequency bandwidth of the gain is about 4.06 MHz, and the phase margin is about 37 degrees. The first-port frequency is about 2.06 kHz, and the second-port frequency is about 2.83 MHz.
FIGS. 7A and 7B show the voltage-gain/frequency curves of the prior art PLL. FIG. 7A represents the input voltage curve at the input terminal of the voltage control oscillator 500. FIG. 7B represents the output at the port 523 of the replica biasing voltage 514. According to the curve in FIG. 7B, when the variable current source 522 provides small currents, an output jitter at port 523 is generated. In addition, FIG. 8A is a conventional input voltage curve of a voltage control oscillator. FIG. 8B is a conventional replica biasing circuit output voltage curve.
Accordingly, as the replica biasing circuit 514 cannot stabilize the output thereof under low-current or low-frequency operations, the output jitter of the voltage control oscillator 500 occurs.